Title

Scheduling and Partitioning Schemes for Low Power Designs Using Multiple Supply Voltages

Document Type

Article

Abstract

This paper presents a time-constrained algorithm and a resource-constrained algorithm to minimize the power consumption with resources operating at multiple voltages. The input to both schemes is an unscheduled data flow graph (DFG), and the timing or the resource constraints. In the paper, partitioning is considered with scheduling in the proposed algorithms as multiple voltage design can lead to an increase in interconnection complexity at layout level. That is, in the proposed algorithms power consumption is first reduced by the scheduling step, and then the partitioning step takes over to decrease the interconnection complexity. Both time-constrained and resource-constrained algorithms have time complexity of o(n 2), where n is the number of nodes in the DFG. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve the power reduction under timing constraints and resource constraints by an average of 46.5 and 20%, respectively.

Disciplines

Computer Engineering | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Systems and Communications

Permissions

Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited