Title

An efficiency measure of FPGA based logic synthesis tools

Document Type

Article

Abstract

In FPGA - based designs, the number of LOgic Cells (LCs) needed is an important criterion to judge whether a desing is good or not. But the total number of LCs needed to implement a circuit differs vastly from tool to tool. Normally, vendor software use more LCs than the theoretical maximum needed by functional decomposition to implement a circuit. Academic software uses less number of LCs. So far, we are aware of any technique that would give a quantitative measure to judge the comparable silicon area efficiency of a logic synthesis tool. This paper presents a technique to calculate the minmax number of logic cells (Q) which are necedssary to implement a logic circuit.

Disciplines

Computer Engineering | Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | Systems and Communications

Permissions

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