Title

A novel multiplexer-based low-power full adder

Document Type

Article

Abstract

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Disciplines

Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | VLSI and Circuits, Embedded and Hardware Systems

Permissions

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