A novel Multiplexer-based Low-power Full Adder

Authors

Yingtao Jiang, University of Nevada, Las VegasFollow
A. Al-Sheraidah, University of Texas at Dallas
Y. Wang, University of Texas at DallasFollow
E. Sha, University of Texas at Dallas
J. G. Chung, Chonbuk National University

Document Type

Article

Publication Date

7-2004

Publication Title

IEEE Transactions on Circuits and Systems II-Express Briefs

Volume

51

Issue

7

First page number:

345

Last page number:

348

Abstract

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF [1] and 10T [4]) and is 64% faster.

Keywords

Integrated circuits--Very large scale integration; Microelectronics--Design; Microelectronics--Power supply; Transistor circuits

Disciplines

Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | VLSI and Circuits, Embedded and Hardware Systems

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

Repository Citation

Jiang, Y., Al-Sheraidah, A., Wang, Y., Sha, E., Chung, J. G. (2004). A novel Multiplexer-based Low-power Full Adder. IEEE Transactions on Circuits and Systems II-Express Briefs, 51(7), 345-348.