Synthesis Scheme for Low Power Designs with Multiple Supply Voltages By Heuristic Algorithms

Document Type

Conference Proceeding

Publication Date

4-5-2004

Publication Title

International Conference on Information Technology: Coding Computing, ITCC 2004

Publisher

Institute of Electrical and Electronics Engineers

First page number:

826

Last page number:

830

Abstract

We present three heuristics synthesis schemes to minimize power consumption with resources operating at multiple voltages under timing and resource constraints. Unlike the conventional methods where only scheduling is considered, all these schemes consider both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve different performance.

Keywords

Algorithm design and analysis; Digital signal processing; Energy consumption; Heuristic algorithms; Integrated circuit interconnections; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Timing; Voltage

Disciplines

Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

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