Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing

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Practical analog layout synthesis techniques have been the subject of active research for the past two decades to address the growing gap between the increasing chip functionality and the design productivity. In this paper, we present a novel macro-cell placement approach following the optimization flow of a genetic algorithm controlled by the methodology of simulated annealing. A process of cell slide is adopted to drastically reduce the configuration space without degrading search opportunities. In addition, this cell-slide process is used to satisfy the symmetry constraints essential for analog layouts. Furthermore, the dedicated cost function captures subtle electrical and geometrical constraints, such as area, net length, aspect ratio, proximity, parasitic effects, etc. required for analog layout and subsequent intellectual property reuse. To study the algorithm parameters, fractional factorial experiments and a meta-GA approach are employed. The proposed algorithm has been tested using several analog circuits. Compared to the simulated-annealing approach, the dominant one currently used for the analog placement problem, the proposed algorithm requires less computation time while generating higher quality layouts, comparable to expert manual placements. Furthermore, our hybrid algorithm and the method of parameter optimization can be readily adapted to different optimization problems across disciplines.


Electrical and Computer Engineering | Engineering | Signal Processing | Systems and Communications


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