Energy Efficient Run-time Incremental Mapping for 3-d networks-on-chip
Document Type
Article
Publication Date
1-1-2013
Publication Title
Journal of Computer Science and Technology
Volume
28
Issue
1
First page number:
54
Last page number:
71
Abstract
3-D Networks-on-Chip (NoC) emerge as a potent solution to address both the interconnection and design complexity problems facing future Multiprocessor System-on-Chips (MPSoCs). Effective run-time mapping on such 3-D NoC-based MPSoCs can be quite challenging, as the arrival order and task graphs of the target applications are typically not known a priori, which can be further complicated by stringent energy requirements for NoC systems. This paper thus presents an energy-aware run-time incremental mapping algorithm (ERIM) for 3-D NoC which can minimize the energy consumption due to the data communications among processor cores, while reducing the fragmentation effect on the incoming applications to be mapped, and simultaneously satisfying the thermal constraints imposed on each incoming application. Specifically, incoming applications are mapped to cuboid tile regions for lower energy consumption of communication and the minimal routing. Fragment tiles due to system fragmentation can be gleaned for better resource utilization. Extensive experiments have been conducted to evaluate the performance of the proposed algorithm ERIM, and the results are compared against the optimal mapping algorithm (branch-and-bound) and two heuristic algorithms (TB and TL). The experiments show that ERIM outperforms TB and TL methods with significant energy saving (more than 10%), much reduced average response time, and improved system utilization.
Keywords
Energy efficiency; Networks-on-Chip; Multiprocessor System-on-Chips; Run-time incremental mapping
Disciplines
Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Electromagnetics and Photonics | Electronic Devices and Semiconductor Manufacturing | Power and Energy | Signal Processing
Language
English
Permissions
Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.
Repository Citation
Wang, X.,
Liu, P.,
Yang, M.,
Palesi, M.,
Jiang, Y.,
Huang, M. C.
(2013).
Energy Efficient Run-time Incremental Mapping for 3-d networks-on-chip.
Journal of Computer Science and Technology, 28(1),
54-71.