Award Date

5-2009

Degree Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

First Committee Member

Yingtao Jiang, Chair

Second Committee Member

Rama Venkat

Third Committee Member

Biswajit Das

Graduate Faculty Representative

Laxmi Gewali

Number of Pages

111

Abstract

Today's emerging communication technologies require fast processing as well as efficient use of resources. This project specifically addresses the power-efficient design of an FFT processor as it relates to OFDM communications such as cognitive radio. The Fast Fourier Transform (FFT) processor is what enables the efficient modulation in OFDM. As the FFT processor is the most computationally intensive component in OFDM communication, the power efficiency improvement of this component can have great impacts on the overall system. These impacts are significant considering the number of mobile and remote communication devices that rely on limited battery-powered operation. This project explores current FFT processor algorithms and architectures as well as optimization techniques that aim to reduce the power consumption of these devices. A floating point as well as a fixed point dynamically size-configurable FFT processor was designed in VHDL for FPGA applications, and power-saving modifications were implemented while analyzing the results.

Keywords

Cognitive radio networks; Digital communications; Electronics; Orthogonal frequency division multiplexing; Wireless communication systems

Disciplines

Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | Systems and Communications

Language

English

Comments

Signatures have been redacted for privacy and security measures.


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