Award Date


Degree Type


Degree Name

Master of Science in Electrical Engineering (MSEE)


Electrical Engineering

First Committee Member

Yingtao Jiang

Second Committee Member

Mei Yang

Third Committee Member

Biswajit Das

Fourth Committee Member

Sajjad Ahmad

Number of Pages



With the ever-increasing demand for high-performance computing systems, on-chip interconnection networks, serving as the communication links in multicore architectures, have become the key to the system performance. Compared with bandwidth-limited power-hungry electrical interconnection networks, optical network-on-chip (ONoC) architectures are emerging as a promising alternative to enable future computing performance gains owing to the recent advancements in silicon photonics. One major issue of ONoC is its insertion loss, which is the optical link loss along the waveguide and through the network. Once the optical power budget is established, the maximum insertion loss through the network can be determined. If insertion loss exceeds optical power budget, the network will fail to transmit and recover the optical data. Moreover, insertion loss also decides the scale of the network since a network with less insertion loss can use more wavelength channels to increase the aggregate bandwidth.

In this thesis, a new methodology to construct ONoC topologies with lower insertion loss is proposed. It is realized by transforming the network structure, which is much simpler and less expensive. First, the insertion loss of two basic types of microring resonator optical switch, which is the key component in the ONoC are analyzed using the coupling model. Three-dimensional FDTD-based simulation is performed to verify the theoretical analysis. Results show that parallel-coupled switch has better performance than cross-coupled switch in terms of insertion loss. Next, the proposed method is applied to the generalized wavelength-routed ONoC, which is built solely with cross-coupled switches. To reduce insertion loss in this network, the first step is to replace the cross-coupled switches with parallel-coupled ones as many as possible, which is denoted as Replaced Parallel Network (RPN). The second step is to replace the rest cross-coupled switches in the RPN with the combination of a parallel-coupled switch and a waveguides crossing, and such network after replacement is denoted as Low Insertion-loss Network (LIN). RPN and LIN are proved to be equivalent to the original network as they use the same number of waveguides and microring resonator switches. Theoretical analysis and numerical results confirm that the average insertion loss of the generalized wavelength-

routed network can be effectively reduced by the proposed method.


insertion loss; microring resonator; optical network-on-chip


Electrical and Computer Engineering