Award Date

May 2017

Degree Type

Thesis

Degree Name

Master of Science in Electrical Engineering (MSEE)

Department

Electrical and Computer Engineering

First Committee Member

Russel J. Baker

Second Committee Member

Peter A. Stubberud

Third Committee Member

Yahia Baghzouz

Fourth Committee Member

Evangelos Yfantis

Number of Pages

88

Abstract

Capacitive sensing is a popular technology employed in billions of products and millions of applications. This Thesis details the design, layout and characterization of an Integrated Circuit (IC) that employs Delta-Sigma Modulation (DSM) for sensing capacitance. The chip, measuring 1.5 mm x 1.5 mm, was designed in On Semiconductor’s C5 process and was manufactured by MOSIS.

The sensing circuit links linearly the ratio of a “test” to a “reference” capacitance to the output of a Delta-Sigma Modulator. The equations that describe the operation of the sensing circuit are derived. Besides the sensing circuit, there is a non-overlapping clock generator that provides the necessary clock signals for the circuit’s operation. There is also some peripheral circuitry that translates the digital output of the sensing circuit to an 8-bit binary number that can be used to calculate “test” capacitance and is immune to power supply voltage variations. The chip can sense any capacitance with an error as little as 0.07 % for some values in the pico-Farad and nano-Farad range by adjusting the reference capacitor and the input clock signal (30 kHz and 30 Hz respectively). The circuit operates on a nominal power supply voltage of 5 V and the maximum power dissipation of the entire circuit is 750 μW.

The chip is also used for two applications, water level sensing and soil moisture content measurement. The capacitive sensor used for these applications is made on PCB and its capacitance is linearly related to water level and moisture content.

Disciplines

Electrical and Computer Engineering

Language

English


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