Handwritten Digit Recognition System on an FPGA
2018 IEEE 8th Annual Computing and Communication Workshop and Conference
Las Vegas, NV
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This paper describes our implementation of a multilayer perceptron (MLP) learning network on a Cyclone IVE field programmable gate array (FPGA). The MLP uses MNIST data, the Modified National Institute of Standards and Technology database of handwritten digits, to train and test the design. Working with 8-bit precision, the FPGA design has similar accuracy and execution time as the 32-bit software solution but with 144 times slower clock frequency. With power consumption being proportional to frequency, the hardware solution provides power savings at no cost in accuracy or performance. Further reducing the precision from 8 to 4 bits only reduces accuracy from 89% to 78%, with area decreasing by 41%. Thus, the FPGA implementation of the MLP learning network offers a high-performance, low power alternative to traditional software methods.
MNIST; FPGA; MLP; Deep learning; Machine learning; Hardware acceleration
Harris, S. L.
Handwritten Digit Recognition System on an FPGA.
2018 IEEE 8th Annual Computing and Communication Workshop and Conference, 2018
Las Vegas, NV: IEEE.