Incorporation of Chopping in Continuous Time K-Delta-1-Sigma Modulator

Document Type

Conference Proceeding

Publication Date

6-25-2021

Publication Title

2021 19th IEEE International New Circuits and Systems Conference, NEWCAS 2021

Publisher

Institute of Electrical and Electronics Engineers

Publisher Location

Tuolon, France

First page number:

1

Last page number:

4

Abstract

A chopping technique in a continuous time K-delta-1-sigma modulator (KD1S) is reported in this paper. It is shown that the presence of the inherent path filter in the proposed technique can significantly improve the performance of the modulator by minimizing the aliased quantization noise. Also reported are how the selection of chopping frequency and its relation to sampling frequency and the trade-offs. To support the theory, a first order K-delta-1-sigma topology was designed in a 180nm CMOS process. Simulations are used to illustrate the validity of the results. The modulator works at a sampling frequency of 1 MHz with an oversampling ratio of 256. It consumes an average current of 61.18 µA from 1.8 V supply. The simulation result shows that there is more than 25dB improvement in the Signal-to-Noise Ratio (SNR) of the KD1S, when chopped at the right frequency.

Keywords

Aliasing; Chopping; Chopping effects; Delta-sigma modulator; FIR DAC; Flicker noise; Integrator; Oversampling; SNR

Disciplines

Digital Circuits

Language

English


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