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This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator that can be used in wireless CDMA receivers. The continuous-time delta-sigma modulator samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The continuous-time delta-sigma modulator was fabricated in a 0.18- m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2 . The delta-sigma modulator's critical performance specifications are derived from the CDMA receiver specifications.


Analog–digital conversion; Analog-to-digital converters; CMOS; Code division multiple access (CDMA); Continuous-time delta-sigma modulation; High-speed integrated circuit; Integrated circuits; Metal oxide semiconductors; Complementary; Modulators (Electronics)


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