An Analysis of Dynamic Element Matching Flash Digital to Analog Converters

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IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing





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Although many dynamic element matching (DEM) digital-toanalog converters (DACs) have identical architectures, analyses of DEM DACs have been specific to the DAC DEM algorithm or based on simulation results. In this paper, a commonly used flash DEM DAC architecture is analyzed. Using this analysis, a DEM DAC’s mean integral nonlinearity (INL), variance of the INL, output signal-to-distortion ratio, output signal-to-(noise plus distortion) ratio, and spurious-free dynamic range can be calculated theoretically. These theoretical measures can be used as criteria for comparing the performance of different DEM algorithms applied to the particular flash DEM DAC architecture analyzed in this paper. As an example, two new DEM algorithms—a barrel shift network controlled by a white stochastic signal and a generalized cube interconnection network (GCN) controlled by a colored stochastic signal—are introduced and compared with two stochastic DEM algorithms: a Benes network and a GCN—both of which are controlled by a white stochastic signal—and one deterministic DEM algorithm called clock-level averaging. In the example, the performance criteria are calculated theoretically and by simulation.


Digital–analog conversion; Digital-to-analog converters; Distortion; Hybrid integrated circuits; Interconnection networks; Mixed analog–digital integrated circuits; Mixed signal circuits; Sigma Delta modulation; Signal processing


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