Title

Location of Processor Allocator and Job Scheduler and Its Impact on CMP Performance

Document Type

Article

Publication Date

4-2012

Publication Title

International Journal of Electronics and Telecommunications

Volume

58

Issue

1

First page number:

9

Last page number:

14

Abstract

High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.

Keywords

Commuting--Energy consumption; Computer architecture; High performance computing; Networks on a chip; Parallel computers

Disciplines

Computer and Systems Architecture | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | VLSI and Circuits, Embedded and Hardware Systems

Language

English

Permissions

Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited

Identifier

DOI: 10.2478/v10177-012-0001-y

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