Scheduling and Optimal Voltage Selection with Multiple Supply Voltages Under Resource Constraints
Integration, the VLSI Journal
First page number:
Last page number:
This paper presents a novel resource-constrained synthesis scheme to minimize power consumption with resources operating at multiple voltages. The inputs to our scheme are (i) unscheduled data flow graph, (ii) library containing a table of delays and supply voltages for the resources and (iii) resource constraints given as the number and the type of functional units to be used. The proposed scheme, with polynomial time complexity, runs in three phases. In the first phase, operations are scheduled to minimize the number of control steps, and in the meantime, they are assigned to resources operating at reduced voltages. In the second phase, operations are clustered to form proper voltage islands to minimize interconnection costs. In the last phase, operations are rescheduled and permanently bound to sources, which will satisfy the given resource constraints. At this point, rescheduling is necessary to minimize the total number of control steps. A number of DSP benchmark circuits have been used to test the proposed algorithm. Depending on the tightness of the resource constraints, significant power reduction can be achieved (an average of 20% and >60% power reduction for tight and loose resource constraints, respectively).
Computer scheduling; Computers--Power supply; Energy consumption; Partitioning
Computer Engineering | Digital Circuits | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | Systems and Communications
Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited
Scheduling and Optimal Voltage Selection with Multiple Supply Voltages Under Resource Constraints.
Integration, the VLSI Journal, 40(2),