FPGA-based Design Using a Generalized Boolean Decomposition Method
International Journal of Electronics
First page number:
Last page number:
A generalized Boolean decomposition algorithm is formulated to map a Boolean function into a network of universal cells capable of implementing any function with a fixed number of inputs and outputs. The method is applied to several standard benchmarks and the results presented. When the algorithm is targeted at a technology-specific multi-input cell structure, the cell count is reduced considerably.
Computer algorithms; Decomposition method; Field programmable gate arrays; Integrated circuits—Very large scale integration; Logic circuits
Computer Engineering | Controls and Control Theory | Electrical and Computer Engineering | Signal Processing | Systems and Communications
Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited
Patel, D. C.
FPGA-based Design Using a Generalized Boolean Decomposition Method.
International Journal of Electronics, 78(4),