Maximizing resource utilization by slicing of superscalar architecture

Document Type

Conference Proceeding


Superscalar architectural techniques increase instruction throughput by increasing resources and using complex control units that perform various functions to minimize stalls and to ensure a continuous feed of instructions to the execution units. This work proposes a dynamic scheme to increase efficiency of execution (throughput) by a methodology called block slicing. This takes advantage of instruction level parallelism (ILP) available in programs without increasing the number of execution units. Implementation of this concept in a wide, superscalar pipelined architecture introduces nominal additional hardware and delay, while offering power and area advantages. We present the design of the hardware required for the implementation of the proposed scheme and evaluate it for the metrics of speed-up, throughput and efficiency.


Bandwidth; Computer architecture; Embedded system; Field programmable gate arrays; Hardware; Logic design; Parallel processing; Processor scheduling; Resource management; Throughput


Electrical and Computer Engineering | Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing | Signal Processing | VLSI and Circuits, Embedded and Hardware Systems


Conference held: Parma, 3-5 Sept. 2008


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