Fuse-N: Framework for unified simulation environment for network-on-chip
Current uni-processor centric modeling methodology does not address the new design challenges introduced by MPSoCs, thus calling for efficient simulation frameworks capable of capturing the interplay between the application, the architecture, and the network. Addressing these new challenges requires a framework that assists the designer at different abstraction levels of system design. This paper concentrates on developing a framework for unified simulation environment for NoCs (fuse-N) which simplifies the design space exploration for NoCs by offering a comprehensive simulation support. The framework synthesizes the network infrastructure and the communication model and optimizes application mapping for design constraints. The proposed framework is a hardware-software co-design implementation using SystemC 2.1 and C++. Simulation results show the various design space explorations that can be performed by our framework.
Computational modeling; Computer networks; Computer simulation; Delay; Design optimization; Network synthesis; Network-on-a-chip; Routing; Space exploration; Throughput
Computer and Systems Architecture | Computer Engineering | Digital Communications and Networking | Electrical and Computer Engineering | Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing
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Fuse-N: Framework for unified simulation environment for network-on-chip.
ITNG 2009 - 6th International Conference on Information Technology: New Generations
Institute of Electrical and Electronics Engineers.