Traffic Aware Scheduling Algorithm for network on Chip

Document Type

Conference Proceeding

Publication Date


Publication Title

ITNG 2009 - 6th International Conference on Information Technology: New Generations, 2009


Institute of Electrical and Electronics Engineers Computer Society

First page number:


Last page number:



Steady advancements in semiconductor technology over the past few decades have lead to researchers have proposed network-on-chip (NoC) as the on-chip communication model. An efficient NoC design methodology is based upon several key design choices, such as: network topology selection, good routing policy and efficient application to NoC mapping. In this paper a novel off-line non-preemptive static traffic aware scheduling (TAS) policy is proposed for hard NoC platforms. The proposed scheduling policy maps the application onto the NoC architecture keeping track of the network traffic, which is generated with every resource and communication path allocation. The main contribution of the proposed algorithm is that the application mapping and scheduling process are handled together and inter-process communication latency are dynamically calculated based on the application mapping and PE interaction. Our TAS algorithm has been evaluated for various design metrics such as application completion time, resource utilization and task throughput. Simulation results show significant improvements over traditional approaches.


Design methodology; Dynamic scheduling; Lead compounds; Network topology; Network-on-a-chip; Resource management; Routing; Scheduling algorithm; Telecommunication traffic; Traffic control


Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Other Electrical and Computer Engineering | Signal Processing




Conference held: Las Vegas, NV, 27-29 April 2009


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