An efficient reconfigurable architecture and implementation of edge detection algorithm using handle-C
Computer manipulation of images is generally defined as digital image processing (DIP). DIP is employed in variety of applications, including video surveillance, target recognition, and image enhancement. Some of the algorithms used in image processing include convolution, edge detection and contrast enhancement. These are usually implemented in software but may also be implemented in special purpose hardware to reduce speed. In this work the canny edge detection  architecture has been developed using reconfigurable architecture and hardware modeled using a C-like hardware language called Handle-C. The proposed architecture is capable of producing one edge-pixel every clock cycle. The hardware modeled was implemented using the DK2 IDE tool on the RC1000 Xilinx Vertex FPGA based board [M. Newman]. The algorithm was tested on standard image processing benchmarks and significances of the result are discussed.
Application software; Computer architecture; Digital images; Electronics packaging; Hardware; Image edge detection; Image processing; Reconfigurable architectures; Target recognition; Video surveillance
Computer and Systems Architecture | Computer Engineering | Controls and Control Theory | Digital Communications and Networking | Electrical and Computer Engineering | Electrical and Electronics | Hardware Systems | Power and Energy | Signal Processing
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Rao, D. V.,
An efficient reconfigurable architecture and implementation of edge detection algorithm using handle-C.
International Conference on Information Technology: Coding Computing, ITCC 2004
Institute of Electrical and Electronics Engineers.