Synthesis scheme for low power designs with multiple supply voltages by heuristic algorithms
We present three heuristics synthesis schemes to minimize power consumption with resources operating at multiple voltages under timing and resource constraints. Unlike the conventional methods where only scheduling is considered, all these schemes consider both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve different performance.
Algorithm design and analysis; Digital signal processing; Energy consumption; Heuristic algorithms; Integrated circuit interconnections; Partitioning algorithms; Processor scheduling; Scheduling algorithm; Timing; Voltage
Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | Systems and Communications
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Synthesis scheme for low power designs with multiple supply voltages by heuristic algorithms.
International Conference on Information Technology: Coding Computing, ITCC 2004
Institute of Electrical and Electronics Engineers.