Fault-tolerant Routing Schemes in RDT(2,2,1)/α Based Interconnection network for networks-on-chip Designs

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Conference Proceeding

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Publication Title

8th International Symposium on Parallel Architectures, Algorithms and Networks, I-SPAN 2005



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It has been well recognized that the fault-tolerance capability is vital for a NoC system, since one faulty link/processor may isolate a large fraction of processors. Continuing from a previous paper where a RDT(2,2,1)/α-based interconnection network for NoC designs was proposed, we investigate fault-tolerant routing schemes on NoC systems featuring a RDT-based interconnection network. In particular, we propose two fault-tolerant routing schemes in the presence of either single link/node failure or multiple link/node failures. The proposed routing schemes are based on deterministic routing. Alternative routes are discovered by properly selecting the intermediate nodes between the source and the destination nodes on the rank tori. As of the single link/node failure case, we show that the number of routers on the detoured route generated by the proposed routing scheme is at most 2 more than the number of routers on the original route.


Computer science; Fault tolerance; Fault tolerant systems; Intelligent networks; Isolation technology; Multiprocessor interconnection networks; Network-on-a-chip; Routing; Transistors; Very large scale integration


Computer Engineering | Digital Circuits | Digital Communications and Networking | Electrical and Computer Engineering | Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing | Hardware Systems | Systems and Communications | VLSI and Circuits, Embedded and Hardware Systems




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