Processor Allocation Problem for NoC-based Chip Multiprocessors

Document Type

Conference Proceeding

Publication Date

4-27-2009

Publication Title

ITNG 2009 - 6th International Conference on Information Technology: New Generations

Publisher

IEEE

First page number:

96

Last page number:

101

Abstract

Chip multiprocessors (CMPs) have become the primary approach to build high-performance microprocessors. Such systems require fast and efficient communication that can only be realized using network on chip (NoC), particularly for large systems. Allocation and management of on-chip processors are also important factors to achieve high efficiency. Designing processor allocator, job scheduler and NoC are major issues for future CMPs. In this paper we analyze architectures of NoC for CMPs. Such NoC parameters as topology, flow control and routing are studied and proposed for CMPs implementation. Modern processor allocation algorithms together with scheduling techniques are reviewed and suggested. Hardware structure of NoC-based CMPs is introduced for the recommended solutions. We propose hardware implementation of processor allocator and job scheduler, and place them together with on-chip processors on the same die.

Keywords

Microprocessor chips; Network routing; Network topology; Network-on-chip

Disciplines

Electrical and Computer Engineering | Electrical and Electronics | Engineering | Signal Processing | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

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