Synthesis of processor allocator for torus-based chip multiprocessors

Document Type

Conference Proceeding


Chip MultiProcessor (CMP) architectures are dominant trend in parallel processing systems. With the number of on-chip processors rising to the hundreds, allocation and management of the processors are also important factor to achieve high efficiency of CMPs. In this paper, the authors study a Processor Allocator (PA) for CMP based on torus Network-on-Chip. The best, IFF and IAS algorithms for mesh-based CMP are presented and their torus extension is proposed. The synthesis of both IFF and IAS allocation techniques for mesh and torus topologies is performed and its results are analyzed. The presented outcomes reveal the significant advantage of the PA driven by bit map algorithms. The mesh-based PA driven by the IFF scheme outperformed the other techniques by good frequency characteristic and low logic utilization. For the torus-based PA only the IFF technique with torus extension remains the reasonable solution, however its performance characteristic is weaker in comparison to the mesh counterpart.


Integrated circuit design; Microprocessor chips; Multiprocessing systems; Network topology; Network-on-chip; Parallel architectures


Electrical and Computer Engineering | Electrical and Electronics | Engineering | Signal Processing | Systems and Communications


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