An Area-time Efficient Architecture for 16 X 16 Decimal Multiplications

Document Type

Conference Proceeding

Publication Date


Publication Title

2013 10th International Conference on Information Technology: New Generations, ITNG 2013, April 15, 2013 - April 17, 2013

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With growing demands of decimal computations in scientific, financial and many other key applications, area-time efficient hardware implementation of decimal arithmetic is desired. In this paper, we present a parallel architecture for the fixed-point decimal multiplications based on the 8421 BCD representation. By reducing the entries of partial product pre-computations and using a tree structure with carry-look ahead adders (CLAs) as opposed to carry-save adders (CSAs), a significant speedup of the partial product generations (PPGs) and partial product accumulations can be achieved, while at the same time, the hardware overhead can be reduced. The × decimal multiplier using the proposed architecture with a TSMC 90nm technology compares favorably against three other best known decimal multiplier designs in terms of delay-area product.


Adders; Algorithm design and analysis; Computer architecture; Delays; Hardware; Pipelines; Throughput


Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Electromagnetics and Photonics | Electronic Devices and Semiconductor Manufacturing | Power and Energy | Signal Processing | Systems and Communications | VLSI and Circuits, Embedded and Hardware Systems




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