Half Baud-rate, Low BER PAM-4 CDR Based on SS-MMSE Algorithm
Document Type
Article
Publication Date
1-1-2016
Publication Title
Electronics Letters
Volume
52
Issue
25
First page number:
2036
Last page number:
2038
Abstract
A hardware-efficient four-level pulse amplitude modulation (PAM-4) clock and data recovery (CDR) circuit for high speed serial links is proposed, following a sign-sign minimum mean square error (SS-MMSE) algorithm. Using a specially designed continuous-sampling slope detector and a dual-stage digital filter, the proposed SS-MMSE CDR can align the clock phase well with the maximum vertical eye opening, as opposed to the conventional Bang-Bang CDR which only finds the midpoint of a symbol, yet requiring extra clock phases or running at higher frequency. Simulation results confirm superior performance and implementation efficiency of this proposed SS-MMSE PAM-4 CDR over the Bang-Bang design. © The Institution of Engineering and Technology 2016.
File Format
File Size
909.73 KB
Language
English
Repository Citation
Liu, P.,
Guo, J.,
Jiang, Y.
(2016).
Half Baud-rate, Low BER PAM-4 CDR Based on SS-MMSE Algorithm.
Electronics Letters, 52(25),
2036-2038.
http://dx.doi.org/10.1049/el.2016.2944
