Interconnection Networks Efficiency in System-on-chip Distributed Computing System: Concentrated Mesh and Fat Tree

Document Type

Conference Proceeding

Publication Date

1-1-2017

Publication Title

Proceedings - 25th International Conference on Systems Engineering, ICSEng 2017

Publisher

Institute of Electrical and Electronics Engineers Inc.

Volume

2017-January

First page number:

277

Last page number:

286

Abstract

Distributed Processing Systems (DPS) take sophisticated tasks as input, divide them into smaller chunks and process in a distributed manner using spread resources. There are many well-known DPS that operate on geographically distributed nodes, but the operating scale for such systems spans till also on-chip architectures. In this paper, we present a concept of distributed processing system for System-On-Chip scale and define the assumptions, architecture, components and show how to build the DPS over SoC. Using the proposed concept, we evaluate the low-level interconnection architectures: concentrated mesh and fat tree - and compare their efficiency with a well-known one - 2D mesh. The proposed DPS is formulated as MIP-style mathematical description, along with energy consumption metric. The properties of each object, abstraction layers and system operation are comprehensively defined. Proposed ideas and solutions are implemented in an experimentation system that is used to research their quality. Research results show that the concentrated mesh is a promising interconnection network suitable to handle the needs of distributed processing systems on a SoC. © 2017 IEEE.

Language

english

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