Hardware design of parallel switch setting algorithm for Benes networks

Document Type

Conference Proceeding

Publication Date

1-1-2017

Publication Title

International Journal of High Performance Systems Architecture

Publisher

Inderscience Enterprises Ltd.

Volume

7

Issue

1

First page number:

26

Last page number:

40

Abstract

Benes/Clos networks have been used in many areas, such as interconnection network in parallel computers, multiprocessors system, and networks-on-chip. The parallel switch setting algorithm is the key to satisfy the requirements of high performance switching networks. The Lee's routing algorithm is by far the most efficient parallel routing algorithm for Benes networks. However, there is no hardware implementation for this algorithm. In this paper, the Lee's routing algorithm is fully implemented in RTL and synthesised. We have refined the algorithm in data structure and initialisation/updating of relation values to make it suitable for hardware implementation. The simulation and synthesis results of the switching setting circuits for 4 × 4 to 64 × 64 Benes networks confirm that the timing, area, and power consumption of the circuit is consistent with the complexity of the Lee's algorithm. To the best of our knowledge, this is the first complete hardware implementation of the parallel switch setting algorithm which can handle all types of permutations including partial ones. Copyright © 2017 Inderscience Enterprises Ltd.

Language

english

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