Award Date

1-1-2000

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering

First Committee Member

Rama Venkat

Number of Pages

97

Abstract

Decreasing feature sizes of advanced ULSI (Ultra large-scale integrated) devices are driven by a desire for improve device performance and an increase in the number of devices on a single wafer. Small feature sizes cause increased resistance, which leads to degraded device performances. Silicides can reduce sheet resistance on poly-silicon lines and shallow junctions. The mostly widely accepted silicide process, Titanium Silicide (TiSi2), was adopted because of its low resistivity. Major limitations of TiSi2 include an inability to form on narrow poly-lines and gate shorting. Cobalt silicide is an alternative to TiSi2 due to its scalability (down to 0.065 mum 2) while providing acceptable sheet resistance, better heat cycle immunity, and good junction leakage characteristics; Key factors to be considered for a silicide process are: junction leakage currents, film uniformity, junction spiking, void formation, sheet resistivity, thermal stability, and agglomeration. There are four process variables in this study: the first rapid thermal anneal (RTA) temperature and ramp rate, the Co and TiN removal time, and the second RTA temperature. (Abstract shortened by UMI.).

Keywords

Characterization; Cobalt; Silicide

Controlled Subject

Electrical engineering

File Format

pdf

File Size

2549.76 KB

Degree Grantor

University of Nevada, Las Vegas

Language

English

Permissions

If you are the rightful copyright holder of this dissertation or thesis and wish to have the full text removed from Digital Scholarship@UNLV, please submit a request to digitalscholarship@unlv.edu and include clear identification of the work, preferably with URL.

Identifier

https://doi.org/10.25669/tmpc-27ba


Share

COinS