Award Date

1-1-2000

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical and Computer Engineering

First Committee Member

Henry Selvaraj

Number of Pages

71

Abstract

The ASIC (Application specific Integrated Circuit) designs grow continuously bigger and bigger. This causes dramatic increase in the simulation run time. It is very hard to simulate these designs because the simulation time has risen from hours to days and weeks. Hardware Embedded Simulation (HES) is a technology that facilitates incremental design verification of ASICs. The FPGAs (Field Programmable Gate Arrays) can play an important role in ASIC design cycle. But it is not possible to fit an entire ASIC design into a single FPGA device. This problem can be solved by partitioning the given design into multiple small size designs (modules) and fitting those modules into multiple FPGAs. The purpose of my thesis is to take a large RTL (Register Transfer Level) design of an ASIC into consideration, write and test the software ("C" code) practically to synthesize each top level module and analyze the size of each module in terms of number of CLBs (Configurable Logic Blocks), I/Os, flip-flops, latches and apply the algorithm to partition it automatically into minimum number of FPGAs.

Keywords

Asic; Designs; Devices; Fpga; Hdl; Large; Multiple; Partitioning; Prototyping; Verification

Controlled Subject

Electrical engineering

File Format

pdf

File Size

1320.96 KB

Degree Grantor

University of Nevada, Las Vegas

Language

English

Permissions

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Identifier

https://doi.org/10.25669/jrm5-17mc


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