Award Date

1-1-2006

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Electrical Engineering

First Committee Member

Venkatesan Muthukumar

Number of Pages

65

Abstract

Superscalar architectural techniques increase instruction throughput from one instruction per cycle to more than one instruction per cycle. Modern processors make use of several processing resources to achieve this kind of throughput. Control units perform various functions to minimize stalls and to ensure a continuous feed of instructions to execution units. It is vital to ensure that instructions ready for execution do not encounter a bottleneck in the execution stage; This thesis work proposes a dynamic scheme to increase efficiency of execution stage by a methodology called block slicing. Implementing this concept in a wide, superscalar pipelined architecture introduces minimal additional hardware and delay in the pipeline. The hardware required for the implementation of the proposed scheme is designed and assessed in terms of cost and delay. Performance measures of speed-up, throughput and efficiency have been evaluated for the resulting pipeline and analyzed.

Keywords

Architecture; Maximizing; Resource; Slicing; Superscalar; Utilization

Controlled Subject

Electrical engineering; Computer science

File Format

pdf

File Size

1597.44 KB

Degree Grantor

University of Nevada, Las Vegas

Language

English

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Rights

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