Award Date


Degree Type


Degree Name

Master of Science (MS)


Electrical and Computer Engineering

First Committee Member

Henry Selvaraj

Number of Pages



The growing interest in the field of logic synthesis targeting Field Programmable Gate Arrays (FPGA) and the active research carried out by a number of research groups in the area of functional decomposition is the prime motivation for this thesis. Logic synthesis has been an area of interest in many universities all over the world. The work involves the study and implementation of techniques and methods in logic synthesis. In this work, a logic synthesis tool has been developed implementing the aspects of general and complete Decomposition method based on functional decomposition techniques [4]. The tool is aimed at producing outputs faster and more efficient than the available software. C++ Standard template library is used to develop this tool. The output of this tool is designed to be compatible with the available vendor software. The tool has been tested on MCNC benchmarks and those created keeping in mind the industry requirements.


Architecture; Decomposition; FPGA; Targeting; Tool

Controlled Subject

Electrical engineering; Computer science

File Format


File Size

1658.88 KB

Degree Grantor

University of Nevada, Las Vegas




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