Award Date

1-1-2008

Degree Type

Thesis

Degree Name

Master of Electrical Engineering (MEE)

Department

Electrical and Computer Engineering

First Committee Member

Henry Selvaraj

Number of Pages

61

Abstract

This thesis presents the architecture and design of a JPEG compressor for color images using VHDL. The system consists of major parts like color space converter, down sampler, 2-D DCT module, quantization, zigzag scanning and entropy coDing The color space conversion transforms the RGB colors to YCbCr color coDing The down sampling operation reduces the sampling rate of the color information (Cb and Cr). The 2-D DCT transform the pixel data from the spatial domain to the frequency domain. The quantization operation eliminates the high frequency components and the small amplitude coefficients of the co-sine expansion. Finally, the entropy coding uses run-length encoding (RLE), Huffman, variable length coding (VLC) and differential coding to decrease the number of bits used to represent the image. The JPEG compression is a lossy compression, since downsampling and quantization operations are irreversible. But the losses can be controlled in order to keep the necessary image quality; Architectures for these parts were designed and described in VHDL. The results were observed using Active-HDL simulator and the code being synthesized using xilinx ise for vertex-4 FPGA. This pipelined architecture has a minimum latency of 187 clock cycles.

Keywords

Compression; HDL; Image; Implementation; JPRG; Pipelined

Controlled Subject

Electrical engineering

File Format

pdf

File Size

1597.44 KB

Degree Grantor

University of Nevada, Las Vegas

Language

English

Permissions

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Identifier

https://doi.org/10.25669/swja-6ku1


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