Award Date

1-1-1990

Degree Type

Thesis

Degree Name

Master of Science (MS)

Department

Computer Science

First Committee Member

Ajoy K. Datta

Number of Pages

148

Abstract

We propose an algorithm for simulating atomic registers, test-and-set, fetch-and-add, and read-modify-write registers in a message passing system. The algorithm is fault tolerant and works correctly in presence of up to (N/2) -1 node failures where N is the number of processors in the system. The high resilience of the algorithm is obtained by using randomized consensus algorithms and a robust communication primitive. The use of this primitive allows a processor to exchange local information with a majority of processors in a consistent way, and therefore to take decisions safely. The simulator makes it possible to translate algorithms for the shared memory model to that for the message passing model. With some minor modifications the algorithm can be used to robustly simulate shared queues, shared stacks, etc. (Abstract shortened with permission of author.).

Keywords

Distributed; Memory; Sharing; System

Controlled Subject

Computer science

File Format

pdf

File Size

4044.8 KB

Degree Grantor

University of Nevada, Las Vegas

Language

English

Permissions

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Identifier

https://doi.org/10.25669/7c4n-g7up


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