Master of Science in Engineering (MSE)
First Committee Member
Venkatesan Muthukumar, Chair
Second Committee Member
Third Committee Member
Graduate Faculty Representative
Number of Pages
Networks-on-Chip (NoCs) have been proposed as a promising solution to complex on-chip communication problems. But there is no public accessible HDL synthesizable NoC framework which connects industrial level cores and runs real applications on them. Moreover, many challenging research problems remain unsolved at all levels of design abstraction; design exploration of NoC architecture for applications, scheduling and mapping algorithms, evaluation of switching, topology or routing algorithm for efficient execution of application and optimizing communication cost, area, energy etc Solution to solve the above problem calls for the development of synthesizable, parameterizable NoC Framework that would evaluate and implement the above outstanding research problems and algorithms with minimum ease and flexibility.
The proposed NoC Framework has been used to specifically evaluate the following algorithms or variations in architecture: i) Evaluate Switching Algorithms compare latency, congestion, area and power of Wormhole (WH) and Store and Forward (SF) switching, ii) Efficient Router Architecture: Proposed an efficient Virtual Channel architecture with loopback for SF routing is introduced to improve throughput, latency and area, iii) Static routing algorithm: Proposed a simple and efficient routing algorithm called “Mirror Routing” for Torus architectures. This helps in reducing congestion and the routing algorithm is also deadlock free, iv) Adaptive Routing Algorithm: Proposed and evaluated an adaptive routing algorithm for WK topology.
The simulation results show Wormhole Routing with better latency than Store and Forward. Area and Power usage is also relatively less for Wormhole Routing. Study on different traffic scenarios with different Virtual Channel architectures in Store and Forward routing shows considerable improvement in latency in Virtual Channel architecture with loopback. Also it is proved that the proposed Mirror Routing algorithm is able to handle a single congestion or fault in routing path. The latency increases with increase in size of Torus structure. The Adaptive routing algorithm proposed for WK Topology results in increase in latency but can be considered in scenarios where the receiver node at the congested link is comparatively slow or when the fault in link is permanent.
Network-on-Chip; Networks on a chip; Router; Routers (Computer networks); Routing (Computer network management); Virtual channel; WK-recursive; Wormhole routing; Wormhole switching
Electrical and Computer Engineering | Systems and Communications | VLSI and Circuits, Embedded and Hardware Systems
University of Nevada, Las Vegas
Suseela, Jaya, "Parameterizable network-on-chip emulation framework" (2010). UNLV Theses, Dissertations, Professional Papers, and Capstones. 714.
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