Location
UNLV SEB Lobby & Auditorium
Start Date
26-4-2013 9:30 AM
End Date
26-4-2013 3:00 PM
Description
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using Vector Thread programming Model. Experimental results have shown that our approach can provide 282 times speedup when compared to a conventional CPU implementation.
Keywords
Computer architecture; Electronic data processing; Metal oxide semiconductors; Complementary; Threads (Computer programs)
Disciplines
Computer Engineering | Computer Sciences | Signal Processing | Systems Architecture | VLSI and Circuits, Embedded and Hardware Systems
Language
English
Included in
Computer Engineering Commons, Signal Processing Commons, Systems Architecture Commons, VLSI and Circuits, Embedded and Hardware Systems Commons
Modeling and Architectural Simulations of the Statistical Static Timing Analysis of the Variation Sources For VLSI Circuits
UNLV SEB Lobby & Auditorium
As CMOS technology scales down, process variation introduces significant uncertainty in power and performance to VLSI circuits and significantly affects their reliability. Although Static-Timing Analysis (STA) remains an excellent tool, current trends in process scaling have imposed significant difficulties to STA. As one of the promising solutions, Statistical static timing analysis (SSTA) has become the frontier research topic in recent years in combating such variation effects. This poster will be focusing on two aspects of SSTA and its applications in VLSI designs: (1) Statistical timing modeling and analysis; and (2) Architectural implementations of the atomic operations (max and add) using Vector Thread programming Model. Experimental results have shown that our approach can provide 282 times speedup when compared to a conventional CPU implementation.