Energy Characteristic of a Processor Allocator and a network-on-chip

Document Type

Article

Publication Date

6-22-2011

Publication Title

International Journal of Applied Mathematics and Computer Science

First page number:

385

Last page number:

399

Abstract

Energy consumption in a Chip MultiProcessor (CMP) is one of the most important costs. It is related to design aspects such as thermal and power constrains. Besides efficient on-chip processing elements, a well-designed Processor Allocator (PA) and a Network-on-Chip (NoC) are also important factors in the energy budget of novel CMPs. In this paper, the authors propose an energy model for NoCs with 2D-mesh and 2D-torus topologies. All important NoC architectures are described and discussed. Energy estimation is presented for PAs. The estimation is based on synthesis results for PAs targeting FPGA. The PAs are driven by allocation algorithms that are studied as well. The proposed energy model is employed in a simulation environment, where exhaustive experiments are performed. Simulation results show that a PA with an IFF allocation algorithm for mesh systems and a torus-based NoC with express-virtual-channel flow control are very energy efficient. Combination of these two solutions is a clear choice for modern CMPs.

Keywords

Algorithms--Data processing; Commuting--Energy consumption; Computer architecture; Networks on a chip; Parallel computers; Parallel scheduling (Computer scheduling)

Disciplines

Computer and Systems Architecture | Computer Engineering | Digital Communications and Networking | Electrical and Computer Engineering | Power and Energy | Signal Processing | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited

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