An Efficiency Measure of FPGA Based Logic Synthesis Tools

Authors

Henry Selvaraj, University of Nevada, Las VegasFollow
Piotr Sapiecha, Warsaw University of Technology

Document Type

Article

Publication Date

2000

Publication Title

Electronics and Telecommunications Quarterly

Volume

46

Issue

4

First page number:

479

Last page number:

491

Abstract

In FPGA - based designs, the number of LOgic Cells (LCs) needed is an important criterion to judge whether a desing is good or not. But the total number of LCs needed to implement a circuit differs vastly from tool to tool. Normally, vendor software use more LCs than the theoretical maximum needed by functional decomposition to implement a circuit. Academic software uses less number of LCs. So far, we are aware of any technique that would give a quantitative measure to judge the comparable silicon area efficiency of a logic synthesis tool. This paper presents a technique to calculate the minmax number of logic cells (Q) which are necedssary to implement a logic circuit.

Keywords

Computer algorithms; Decomposition method; Field programmable gate arrays; Logic circuits

Disciplines

Computer Engineering | Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Power and Energy | Signal Processing | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or use interlibrary loan to garner a copy of the article. Publisher copyright policy allows author to archive post-print (author’s final manuscript). When post-print is available or publisher policy changes, the article will be deposited

Repository Citation

Selvaraj, H., Sapiecha, P. (2000). An Efficiency Measure of FPGA Based Logic Synthesis Tools. Electronics and Telecommunications Quarterly, 46(4), 479-491.