Design and Analysis of High Performance Multistage Interconnection networks

Document Type

Article

Publication Date

1-1997

Publication Title

IEEE Transactions on Computers (TC)

Volume

46

Issue

1

First page number:

110

Last page number:

117

Abstract

Small switching elements are the key components of multistage interconnection networks (MINs) used in multiprocessors and in high speed switching fabrics. Clock design for synchronous MINs is an important issue. The existing models assume that the clock period consists of two parts. The control messages are transferred between switching stages during the first part, and the actual data transfer takes place during the second part. We propose a new control design for single queue MINs that reduces the duration of the clock period by making use of output buffers and acknowledgments. The reduction in the clock period comes from the addition of two-unit output buffers, introducing a sophisticated hardware control mechanism, and sacrificing the FIFO feature. We develop an analytical model to compare its performance with the existing designs reported in the literature. We validate our model with extensive simulation studies.

Keywords

Computer networks; Engineering--Computer networks; Multiprocessors

Disciplines

Computer and Systems Architecture | Computer Engineering | Digital Communications and Networking | Electrical and Computer Engineering

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

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