Building a Multi-FPGA-based Emulation Framework to Support networks-on-chip Design and Verification

Authors

Yangfan Liu, Zhejiang UniversityFollow
Peng Liu, Zhejiang UniversityFollow
Yingtao Jiang, University of Nevada, Las VegasFollow
Mei Yang, University of Nevada, Las VegasFollow
Kejun Wu, Zhejiang UniversityFollow
Weidong Wang, Zhejiang UniversityFollow
Qingdong Yao, Zhejiang UniversityFollow

Document Type

Article

Publication Date

10-2010

Publication Title

International Journal of Electronics

Volume

97

Issue

10

First page number:

1241

Last page number:

1262

Abstract

In this article, we present a highly scalable, flexible hardware-based network-on-chip (NoC) emulation framework, through which NoCs built upon various types of network topologies, routing algorithms, switching protocols and flow control schemes can be explored, compared, and validated with injected or self-generated traffic from both real-life and synthetic applications. This high degree of scalability and flexibility is achieved due to the field programmable gate array (FPGA) design choices made at both functional and physical levels. At the functional level, a NoC system to be emulated can be partitioned into two parts: (i) the processing cores and (ii) the network. Each part is mapped onto a different FPGA so that when there is any change to be made to any one of these parts, only the corresponding FPGA needs to be reconfigured and the rest of the FPGAs will be left untouched. At the physical level, two levels of interconnects are adopted to mimic NoC on-chip communications: high bandwidth and low latency parallel on-board wires, and high-speed serial multigigabit transceivers available in FPGAs. The latter is particularly important as it helps the proposed NoC emulation platform scale well with the size increase of the NoCs.

Keywords

Computer networks; Field programmable gate arrays; Networks on a chip; Switching theory--Data processing

Disciplines

Computer Engineering | Digital Circuits | Digital Communications and Networking | Electrical and Computer Engineering | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

Repository Citation

Liu, Y., Liu, P., Jiang, Y., Yang, M., Wu, K., Wang, W., Yao, Q. (2010). Building a Multi-FPGA-based Emulation Framework to Support networks-on-chip Design and Verification. International Journal of Electronics, 97(10), 1241-1262.