Overlay-NoC and H-Phy Based Computing Using Modern Chip MultiProcessors
Document Type
Conference Proceeding
Publication Date
5-6-2012
Publication Title
International Conference on Electro/Information Technology (EIT), 2012
Publisher
IEEE
First page number:
1
Last page number:
6
Abstract
Constant growth in demand for computational power requires advances in the internal mechanisms of multiprocessor computing structures. Such architectures may include many (sometimes, even millions of) processors performing processing tasks. Each technique that increases efficiency leads to significant benefits in operational energy and task execution time. Due the scale of multiprocessor computing structures, the importance of achieving faster and efficient systems is invaluable. In this paper, we present two different approaches for processing tasks on multiprocessor architectures: Hardware-Physical (H-Phy) and Overlay- Network-on-Chip (Overlay-NoC). Both methods are described and compared. We also present the research plan, models, simulation assumptions, and results of research. The paper is summarized with conclusions and future work plan.
Keywords
CMP; Computer simulation; Multiprocessors; Overlay-NoC; Simulation system
Disciplines
Computer and Systems Architecture | Computer Engineering | Electrical and Computer Engineering | Engineering
Language
English
Permissions
Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.
Repository Citation
Chmaj, G.,
Zydek, D.,
Elhalwagy, Y. Z.,
Selvaraj, H.
(2012).
Overlay-NoC and H-Phy Based Computing Using Modern Chip MultiProcessors.
International Conference on Electro/Information Technology (EIT), 2012
1-6.
IEEE.