Title

A SS-CNN on an FPGA for Handwritten Digit Recognition

Document Type

Conference Proceeding

Publication Date

10-10-2019

Publication Title

2019 IEEE 10th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON)

Publisher

Institute of Electrical and Electronics Engineers

Publisher Location

New York, NY

First page number:

88

Last page number:

93

Abstract

This paper describes a Super-Skinny Convolutional Neural Network (SS-CNN) and its implementation on a Cyclone IVE field programmable gate array (FPGA), for handwritten digit recognition. This SS-CNN performs state-of-the-art recognition accuracy but with fewer layers and less neurons. Using parameters with 8 bits of precision, the FPGA solutions of this SS-CNN show no recognition accuracy loss when compared to the 32-bit floating point software solution. In addition to high recognition accuracy, both of the proposed FPGA solutions are low power and require little FPGA area. The proposed hardware solutions indicate a 67 to 355 times power savings potential when compared to the software solution. Thus, our SS-CNN provides a high-performance, low computation demands, hardware friendly, and power efficient solution.

Keywords

SS-CNN; FPGA; MNIST; Deep learning; Machine learning; Hardware acceleration

Disciplines

Artificial Intelligence and Robotics | Electrical and Computer Engineering

Language

English

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