Synthesis Scheme for Low Power Designs with Multiple Supply Voltages By Tabu Search

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Conference Proceeding

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Publication Title

2004 IEEE International Symposium on Circuits and Systems



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In this paper, a tabu search-based behavior level synthesis scheme is proposed to minimize power consumption with resource operating at multiple voltages under the timing and the resource constraints. Unlike the conventional methods where only scheduling is considered, our synthesis scheme considers both scheduling and partitioning simultaneously to reduce power consumption due to the functional units as well as the interconnects among them. More importantly, our approach tends to efficiently address a few practical layout problems inherent to multiple voltage designs. In particular, we have configured our solutions as a three-tuple vector to account for both the timing and the partition. Cycling of the same solutions is prevented by applying a tabu list with an update mechanism enhanced with an aspiration function. In this way, the algorithm can search a large solution space with modest computation effort and fast convergence rate. Experiments with a number of DSP benchmarks show that the proposed algorithms achieve an average power reduction by 49.6%.


Algorithm design and analysis; Energy consumption; Integrated circuit interconnections; Minimization; Polynomials; Power engineering computing; Scheduling algorithm; Throughput; Timing; Voltage


Controls and Control Theory | Electrical and Computer Engineering | Electrical and Electronics | Electromagnetics and Photonics | Electronic Devices and Semiconductor Manufacturing | Power and Energy | Signal Processing




Conference held: 23-26 May 2004


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