On a web-graph-based micronetwork architecture for SoCs
International Journal of Computers and Applications
First page number:
Last page number:
The Network-on-Chip (NoC) concept has been identified as an attractive solution to the ever-increasing interconnect problem in complex System-on-Chip (SoC) designs. In this paper, we propose a highly scalable topology structure for NoC designs based on the web graph. This topology, named as Spidernet, is compared favourably to other five popular NoC topologies, including mesh, torus, fat tree, octagon, and spidergon in terms of node degree, network diameter, connection degree, average most short-circuit path, and average shortest wire length. We further propose a 2D layout design for Spidernet, and experiment results have confirmed its superiority over layouts derived from the above five competing topologies.
Controls and Control Theory | Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing | Power and Energy | VLSI and Circuits, Embedded and Hardware Systems
Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.
On a web-graph-based micronetwork architecture for SoCs.
International Journal of Computers and Applications, 30