On a web-graph-based micronetwork architecture for SoCs

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The Network-on-Chip (NoC) concept has been identified as an attractive solution to the ever-increasing interconnect problem in complex System-on-Chip (SoC) designs. In this paper, we propose a highly scalable topology structure for NoC designs based on the web graph. This topology, named as Spidernet, is compared favourably to other five popular NoC topologies, including mesh, torus, fat tree, octagon, and spidergon in terms of node degree, network diameter, connection degree, average most short-circuit path, and average shortest wire length. We further propose a 2D layout design for Spidernet, and experiment results have confirmed its superiority over layouts derived from the above five competing topologies.


Controls and Control Theory | Electrical and Electronics | Electronic Devices and Semiconductor Manufacturing | Power and Energy | VLSI and Circuits, Embedded and Hardware Systems


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