Title

Placement algorithm in analog-layout designs

Document Type

Article

Publication Date

10-2006

Publication Title

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volume

25

Issue

10

First page number:

1889

Last page number:

1903

Abstract

Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements

Keywords

Analogue integrated circuits; Circuit optimization; Genetic algorithms; Integrated circuit layout; Simulated annealing

Disciplines

Electrical and Computer Engineering | Engineering | Signal Processing | Systems and Communications

Language

English

Permissions

Use Find in Your Library, contact the author, or interlibrary loan to garner a copy of the item. Publisher policy does not allow archiving the final published version. If a post-print (author's peer-reviewed manuscript) is allowed and available, or publisher policy changes, the item will be deposited.

Identifier

DOI: http://dx.doi.org/10.1109/TCAD.2005.860957

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