International Journal of Electronics and Telecommunications
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High Performance Computing (HPC) architectures are being developed continually with an aim of achieving exascale capability by 2020. Processors that are being developed and used as nodes in HPC systems are Chip Multiprocessors (CMPs) with a number of cores. In this paper, we continue our effort towards a better processor allocation process. The Processor Allocator (PA) and Job Scheduler (JS) proposed and implemented in our previous works are explored in the context of its best location on the chip. We propose a system, where all locations on a chip can be analyzed, considering energy used by Network-on-Chip (NoC), PA and JS, and processing elements. We present energy models for the researched CMP components, mathematical model of the system, and experimentation system. Based on experimental results, proper placement of PA and JS on a chip can provide up to 45% NoC energy savings.
Assignment; CMP; Energy; High performance computing; JS; Multiprocessors; PA
Computer and Systems Architecture | Computer Engineering | Electrical and Computer Engineering | Engineering
Copyright De Gruyter Open. Used with permission.
Location of Processor Allocator and Job Scheduler and its Impact on CMP Performance.
International Journal of Electronics and Telecommunications, 58(1),