A 20 GHz High Speed, Low Jitter, High Accuracy and Wide Correction Range Duty Cycle Corrector
K. Bhatia, T. Buchner, D. Zhao, R. Sridhar (Eds.)
International System on Chip Conference
IEEE Computer Society
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Duty-cycle correctors (DCCs) are employed in most high-speed VLSI systems to calibrate the clock duty-cycle at 50% to reduce the deterministic jitter introduced by duty-cycle distortion. An all-analogue feedback DCC circuitry with high working frequency, low jitter, high accuracy, and wide correction range is proposed in this paper. A common mode voltage adjuster and an active feedback amplifier are used to support the DCC to work at a high frequency up to 20 GHz with a wide correction range from 20% to 80%. On the feedback path, a second order duty cycle detector scheme is adopted including a low pass filter and an integrator to significantly reduce the jitter in the output clock and ensure high correction accuracy. Through simulation using 65 nm TSMC CMOS technology, the output duty cycle is corrected to 50±0.3% over the input duty-cycle range of 20-80% for 12.5-20 GHz. The DCC consumes 5.2 mW at 16 GHz using a 1.0 V supply voltage, and has a 572 fs peak-to-peak jitter and a 249 fs RMS jitter. © 2015 IEEE.
A 20 GHz High Speed, Low Jitter, High Accuracy and Wide Correction Range Duty Cycle Corrector. In K. Bhatia, T. Buchner, D. Zhao, R. Sridhar (Eds.),
International System on Chip Conference, February
IEEE Computer Society.