A Scalable Parameterized NoC Emulator Built Upon Xilinx Virtex-7 FPGA

Document Type

Conference Proceeding

Publication Date


Publication Title

Proceedings - 25th International Conference on Systems Engineering, ICSEng 2017


Institute of Electrical and Electronics Engineers Inc.



First page number:


Last page number:



A number of critical design decisions, such as network topology, buffer sizes, flow control mechanism and so on so forth, have to be evaluated in any NoC the design. Designs and verifications of NoCs are based on either software simulations, which are extremely slow and inaccurate for complex models, or hardware emulations using low/midclass FPGAS, where the scalability of the NoC system is intensively restricted by the limited on-chip resources. In this paper, we implement a parameterized NoC emulation system, capable of verifying complete functionality of routers and monitoring network performance and buffer usages in real time, on a hardware platform featuring a super large FPGA chip, Xilinx Virtex-7. This FPGA-based emulator also shall be configured to support multiple routing algorithms and packet transferring mechanisms. Compared to the existing emulators, it requires less user effort to measure the performance under various application scenarios, and it scales well to emulate large NoC designs. Currently, this emulator has been used to study NoCs with sizes of 4x4 and 8x8. For the case of 4×4 (8×8) NoC emulator, data transfers between routers can run at over 50MHz, and only occupies about 6% (25%) of the FPGA logic block resources. © 2017 IEEE.



UNLV article access