FPGA Implementation for Epileptic Seizure Detection Using Amplitude and Frequency Analysis of EEG Signals

Document Type

Conference Proceeding

Publication Date


Publication Title

Proceedings - 25th International Conference on Systems Engineering, ICSEng 2017


Institute of Electrical and Electronics Engineers Inc.



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Patients with epilepsy (a central nervous system disorder) suffer from frequent seizures that occur at unpredictable times without any warning. Therefore, it is necessary to identify the occurrence of seizure in an epileptic patient and prevents patients from SUDEP (SUDDEN UNEXPLAINED DEATH IN EPILEPSY). Prediction of epileptic seizure through analysis of scalp EEG signal which is the measure of the brain's electrical activity avoid aggressive situation of epileptic patients during their seizure. This problem is challenging because the brain's electrical activity is composition of numerous classes with overlapping characteristics which vary significantly across patients. It is critical for separating seizure from other types of brain activity. In this proposed method, seizure detection process is implemented in FPGA using two main parameters of EEG signal such as frequency and amplitude which show variations during seizure. Input signal for this work was obtained from CHB-MIT database. The samples of input EEG signals were obtained in the form of .mat file for the duration of 10 seconds. This input file sample values of EEG signal are digitized which is in the form of sign magnitude representation for further processing in FPGA. Signals are used in text file format for Verilog programming. The first bit (MSB bit) represents sign of that particular sample. The frequency of the input signal was found using zero crossing counters. This count value was compared with general brain wave criteria. Similarly for amplitude level analysis, the remaining bits of input sample were compared with validation values. If there is any large deviation in any one of this comparisons found, then the signal abnormality can be predicted. After implementation, 82% of LUTs and 14% of registers were utilized. Timing summary for implementing this proposed work is obtained as 13.568ns. © 2017 IEEE.



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