Design of High Performance CMOS Logic Circuits with Low Temperature Sensitivity
2017 International Conference on Computer Systems, Electronics and Control (ICCSEC)
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Both absolute delays and delay variations of nanoscale CMOS logic circuits, more than ever, are so heavily dependent on the thermal environment; a logic circuit operating at a high temperature, say 90°C, can see its speed drop to just half of that at 0°C. In this paper, we show two circuit techniques that can be employed to counter such severe circuit performance degradation introduced by thermal effects. First and foremost, temperature-insensitive circuit designs tend to favor implementations that use gates with smaller fan-ins (≤ 4) and have shorter logic paths. Next, the thermal-induced delay penalty can be further reduced by powering logic circuits with temperature adaptive power supplies as proposed in our prior study. Experiments on various benchmark circuits, implemented with a 45nm CMOS technology, have confirmed that, when a single fixed power supply is employed, both absolute circuit delays and temperature-induced delay variations can be reduced by more than 20% as the circuits are implemented using logic gates with small fan-ins and short logic paths. Provided a CTAT -like adaptive voltage supply to replace the single fixed power source, the same circuits will experience even smaller delay variations that fall into the range of 15%~30% for temperature varies between 0°C and 90°C, a sharp contrast to 60%~100% delay variations observed in logic circuits powered by a single constant power supply.
High performance VLSI circuits; Temperature effect; Delay; Fan-in; Logic depth; Power supply
Electrical and Computer Engineering
Design of High Performance CMOS Logic Circuits with Low Temperature Sensitivity.
2017 International Conference on Computer Systems, Electronics and Control (ICCSEC), 2017